This course will give you an in-depth understanding of the inner-workings of modern digital computer systems and tradeoffs present at the hardware-software interface. You will get an understanding of the design process in the context of a complex hardware system, practical experience with computer-aided design tools, and running your designs on real hardware.
Topics include: Instruction set design, computer arithmetic, controller and datapath design, cache and memory systems, input-output systems, networks interrupts and exceptions, pipelining, performance and cost analysis, computer architecture history, and a survey of advanced architectures.
A series of computer design project labs are the centerpiece of the course. The project labs are team projects, with 4-5 students per team. We will implement a major subset of the MIPS architecture three times: once in a single-cycle CPU design, once in a pipelined CPU design, and once in a pipelined CPU with caches and a DRAM controller. Our implementations will be mapped to the gate level and run on FPGA hardware, and will be verified (read: graded by the TAs) using a suite of tricky assembly language programs that test adherence to the MIPS ISA.
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